Many types of computing memory, including various types of Random Access Memory (RAM), are formed from arrays of individual memory devices. A small memory chip may include thousands or millions of individual memory-containing cells, while gigabit chips may include billions of cells. Because the cells are replicated many times, the physical size of an individual memory device and the spacing between cells may markedly impact how many memory devices can be included in a chip.
One type of memory structure that optimizes inter-cell spacing in some applications is the crossbar memory array. Some crossbar arrays include a set of parallel word lines and a set of parallel bit lines. The word lines may extend at right angles to the bit lines horizontally and be offset from the bit lines vertically. At each intersection, a memory device may extend vertically between the intersecting word line and the corresponding bit line. The memory device is electrically coupled to the intersecting word line and bit line, which allows the memory device to be uniquely addressed for reading and/or writing using the coupled lines.
However, while the word line and bit line may select a particular memory device, other current paths may exist between the word line and the bit line through other unselected memory devices. Sneak current through these other paths may contribute to efficiency losses, reduced performance, and reduced read/write accuracy in the memory chip.